The present invention relates to the field of semiconductor technology. Embodiments of the invention relate to integrated circuit package structures and manufacturing methods.
Wafer level ball grid array package (WLBGA) is an advanced packaging technology. Due to its ability to save volume and allow maximum engagement requirement, WLBGA has been widely used. However, the inventors have found that, in devices having small geometries, existing WLBGA technologies suffer from a number of drawbacks. These drawbacks can include cracking in a passivation layer overlying the pads due to stress caused by an organic polymer covering the device. As a result, the bonding pads can be exposed or eroded, leading to chip failures. This is a typical problem in the conventional chip package integration process.
Further, in more advanced packaging technologies, the device size is further reduced and the thermal budget is higher. Therefore, the film stress becomes relatively larger, and the problems described above can become more severe.
Therefore, there is an urgent need for a packaging technology that is capable of alleviating the problem of the passivation layer cracking.